1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device in which an electronic circuit is formed on a semiconductor substrate or semi-insulated substrate and, more particularly, to an emitter-coupled logic (hereinafter referred to as "ECL") circuit operable at a high processing speed.
2. Description of the Prior Art
FIG. 1 shows a typical example of a conventional ECL circuit used as an inverter, to which the present invention relates. In FIG. 1, the ECL circuit comprises a differential pair of transistors Q1 and Q2 whose emitters are connected together; load resistors R.sub.L connected to the collectors of the transistors Q1, Q2, respectively; a constant current source formed by a transistor Q3, a resistor R.sub.E and a first constant voltage source V.sub.CS1 ; a reference constant voltage source V.sub.REF ; and an emitter follower formed by transistors Q4, Q5 and a second constant voltage source V.sub.CS2. In addition, the transistor Q5 and the constant voltage source V.sub.CS2 may be replaced by a resistor.
With such a conventional ECL circuit (an inverter) as illustrated and described above, when the level of an input signal changes from high to low, the output transistor Q4 turns ON so that a load capacitance C.sub.L is charged, whereby the level of an output changes from a low to a high level (pull-up). On the other hand, when the input level changes from low to high, the transistor Q4 turns OFF while discharging electric charges accumulated in the load capacitance C.sub.L through an output resistance of the transistor Q5, thus the output level changes from a high to a low level (pull-down). Time required for the pulling-down is determined according to a time constant decided by a load capacitance and an output resistance. Therefore, the time period required for the pulling-down is longer than that required for the pulling-up, which is a disadvantage in this example of the conventional circuit. The larger the load capacitance, the more significant disadvantage occurs. FIG. 2 depicts a SPICE simulation result for an input/output voltage waveform where a bias current of the paired differential transistors Q1, Q2 is 3 mA, a load resistance is 160 .OMEGA. (hence a logical amplitude is 480 mV), a bias current of the emitter follower is 3 mA, a fan-in is 1, a fan-out is 1, and a load capacitance is 0.4 pF. As shown in FIG. 2., by using device parameters corresponding to those of the latest silicon bipolar transistors, there is obtained a simulation result including a pull-up delay time of 40 picoseconds (psec) and a pull-down delay time of 50 psec.
In the conventional ECL circuits, a pull-down delay time is restricted by the time constant determined by a load capacitance C.sub.L and an output resistance of the transistor Q5, so that it is disadvantageously longer than a pull-up delay time. The disadvantage is particularly significant in the case where the load capacitance is large. This is one of problems to be solved by the invention, in the conventional ECL circuits.